There are many well-known microelectronic packages with stacked chips within a housing, e.g., made of a mold compound. The chips, also called silicon dies, are stacked face up or face down with an adhesive and are electrically connected with a base substrate via wire loops. An example of a stacked chip assembly on a substrate is known from U.S. Patent Publication No. 2003/0159773 A1, which is incorporated herein by reference. There are chips with different dimensions mounted one over another such that the chip with the smaller dimensions is mounted on a chip with larger dimensions. Between the chips is arranged an adhesive. A chip with smaller dimensions must be mounted on a base chip because the rim portion of the base chip is provided with bond pads for electrical connections. These bond pads are connected with contact pads on the substrate with wire loops.
It seems to be clear that the necessity of chips with different dimensions leads to more costs for the assembling process since the mounting tools must be able to mount chips with different outer dimensions.
It is also well-known to realize a stack of individual chips with equal dimensions on a substrate with a spacer between the chips. The first chip is mounted on the substrate by chip bonding with an adhesive or a tape and then a spacer with smaller dimensions is mounted on the first chip. The spacer must have smaller dimensions than the first chip. Then a second chip with equal dimensions is mounted on the spacer and so on. At least the several chips are connected to the substrate with wire loops. Such wire loops are realized with a wire-bonding tool. Alternatively, the wire loops can be performed after each chip bond process.
Such a stack of chips has a comparatively big height, which is contrary to the recent development to produce chip assemblies with a very low height. The reason for the big height are the spacers between the stacked chips. These spacers must have a thickness sufficient to realize a space between the chips, which allows wire bonding, or which secures that the realized wire bond loop does not have the risk for a shortcut to the chip mounted above the lower chip.
A similar stack for a memory module is described in the German laid open application DE 102 51 530 A1 and counterpart U.S. Pat. No. 6,927,484, both of which are incorporated herein by reference. The stacked chips each are provided with two center rows of bond pads and reroute layers to the rim part. Each bond pad is connected with an appropriate reroute layer by a wire loop. A first chip is die bonded on a substrate face up. The central part of the chip is provided with a mold compound with an upper flat surface for mounting a second chip by chip bonding with an adhesive tape. This chip has the same construction as the first chip. Each reroute layer of the chips is connected with the metallization of the substrate (copper wiring) by wire loops. Finally the stacked die assembly is covered by a mold compound such that a housing is the result.
The total height of such assemblies can be reduced in limitations by thinning the chips before assembling them in a stack but this produces the risk of silicon chip damages during transportation and test handling and assembling on bare chip package construction. Especially the edges of the chips are very sensitive.
From the German laid open application DE 102 01 204 A1, and counterpart U.S. Patent Publication No. 2005/0064630, both of which are incorporated herein by reference, a means for protecting the edges of a bare chip after assembling on a substrate is known. An encapsulant encloses the edges of the silicon chip thereby protecting the edges of the chip from mechanically caused damages. This is not suitable for protecting the chip during handling on the assembling process. Also, it is not possible to use the encapsulant as a carrier for contact elements or a reroute layer.